The invention generally relates to wireless communication systems, and relates in particular to wireless transceiver systems for use in telecommunications.
Conventional wireless communications systems include one or more wireless transceivers, each wireless transceiver supporting a particular communications standard (or air interface). Each wireless transceiver typically includes a radio frequency circuit that converts baseband analog signals to radio frequency signals and communicates with a cellular network via an antenna. Each wireless transceiver also typically includes an analog baseband unit that converts the baseband analog signals to baseband digital signals. The wireless transceiver must communicate with a digital baseband processing system that includes one or more processors, either digital signal processors (DSPs) or micro-controller units (MCUs), for encoding/decoding the baseband digital data and controlling the timing of the wireless transceiver(s).
Wireless communications systems that support more than one mode (or standard) of operation typically include a plurality of wireless transceivers, each of which may need to be operated at a different clock frequency. While some systems may employ a plurality of separate clocks (e.g., crystals), such a solution may be too expensive with regard to manufacturing cost and circuit board real estate, so it is desirable to have the wireless communication system operate from a single clock source. For a wireless communications system that supports more than a single communications standard, a multi-mode wireless communications system, the system clock must be able to support the timing requirements of all of the multiple wireless interfaces in parallel as well as provide a reference clock for the digital baseband processing system. To support multiple communications standards, typically, the system clock must be run at the least common multiple of the reference clocks for all of the individual wireless interfaces. For example, a multi-mode wireless communication system supporting the 3GPP GSM and WCDMA (FDD) standards would require a 1.248 Ghz clock to support both the GSM reference clock (13 Mhz) and the WCDMA reference clock (3.84 Mhz), using a single system clock. In most cases, the frequency of the single system clock is too high for use as the reference clock for the digital baseband processing system.
There is a need, therefore, for an efficient and economical timing system for use in a wireless communications system.